The Internet Protocol (IP) is moving communications into a new era of all-IP
integrated systems. Enterprises are demanding Voice-over-IP (VoIP) services
to save costs as well as to achieve communication convergence. A VoIP
gateway is a device that interfaces analog telephones with an IP-based
network. The primary functions of a VoIP gateway is the translation of the
analog telephone signals into a control signaling protocol as well as the
voice packetization. VoIP is an emerging market where System-on-Chip (SOC)
is developed. A SOC is a complete system on an integrated circuit (IC) that
combines software running on embedded processor cores and hardware
intellectual property. Nowadays, vendors offer a set of powerful tools and
intellectual property blocks for designing complete and flexible System-on-
Programmable-Chip (SOPC) in a very short time.
This work presents the development of a low-cost and small VoIP gateway
using the SOPC design methodology, and it also involves the study of
different Power-over-Ethernet (PoE) solutions. This appliance is aimed to be
used as a network test instrument within enterprise infrastructures. The
Altera Cyclone II low-cost FPGA family and Si3210 ProSLIC are selected as
the development platforms because this application is targeted to moderate
volumes of productions, and also it is not able to afford risks and long
design time.
The design flow starts with the definition of a clear system model, followed
by hardware and software co-design, and eventually prototyping and
verification. This design actually exploits the synergism of hardware and
software inside a single FPGA platform. The processes described in the
system model are split in hardware and software. Thereafter, dedicated
digital hardware blocks are implemented with VHDL to accelerate voice
packetization, whereas a C/C++ program implements the main VoIP signaling
protocol ? Session Initiation Protocol (SIP).
Altera SOPC Builder version 5.0 is employed to create the system
architecture. The Nios II soft-processor core and set of on-chip peripherals
are put together using a flexible interconnection bus structure ? the Avalon
Switch Fabric. Then, embedded software is designed to run over this
architecture. It is built up and debugged using the Nios II integrated
development environment (IDE). In addition, the program comprises of a group
of tasks based on the popular MicroC/OS-II real time operating system
(RTOS), which makes use of a lightweight TCP/IP stack (lwIP) for handling
network applications.
Finally, in order to verify the system functionality, the system is
prototyped with the Altera Nios II Development Board that has a Cyclone II
FPGA and the Si321xPPT-EVB. First, the designed architecture is configured
into the FPGA, and later the embedded software is also downloaded on the
evaluation board. Additionally, a ProSLIC device is employed to interface
the SOPC inside the FPGA with an analog te...
