Implementation and Design of a Bit-Error Generator and Logger for Multi-Gigabit Serial Links

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Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higherspeed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems needto be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errorsin a controlled way.A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has beendeveloped. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of thehardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC ishandled with a UART. The final implementation can handle four parallel one way links, or two full duplex lin...