The goal of this thesis was to design a programmable Address Lookup unit for
use in the forwarding engine in a network device such as a switch or a
router.
A solution with a special designed processor core with a optimized
Instruction Set, an I/O processor for accesses to external memory and a
sample of a network software was designed and mapped to a multiprocessor
architecture. The multiprocessor architecture implements the same features as
in the current non programmable hardware Address Lookup unit, and adds the
possibility to upgrade the implementation to meet new features due to the new
property of programmability.
Three multiprocessor architectures, the Parallel multithreaded multiprocessor
architecture, the Macro pipeline RISC multiprocessor architecture and the
Superpipeline VLIW multiprocessor architecture, was selected out as the most
suitable implementation architectures. An estimated implementation area for
the multiprocessor architectures when meeting the current Address Lookup
units performance requirements were calculated. The multiprocessor
architectures were compared against each other on the issues of performance
and area scalability, where the Superpipeline VLIW multiprocessor
architecture was found to be the best implementation platform for the
programmable Address Lookup unit.
The Superpipeline multiprocessor architecture implementation was built on two
basic units, a VLIW processor and an I/O processor. These two basic units was
designed, implemented, verified and synthesized. The result of this synthesis
was compared with the calculated values made during the target architecture
evaluation.
For the VLIW processor the estimated implementation area was calculated to
0.141405 mm2 and the final synthesis to 0.156647 mm2, a difference of 11%.
The difference was analyzed to depend on the control logic added to the final
version of the VLIW processor. For the I/O processor the estimated
implementation area was 0.80800 mm2 and the final synthesis 0.106653 2, a
difference of 32%. The difference was analyzed to depend on multiplexers
added to the final version of the I/O processor. Finally a small
Superpipeline, holding eight VLIW processors and two I/O processors, was
implemented and synthes...
